ARM AMBA NIC-301 manuales

Arm AMBA NIC-301 Manual de usuario (24 paginas)

Marca: Arm | Categoria: Redes | Tamaño: 0.65 MB |

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1 Reducing latency

1

2 Vybrid architecture

2

3 Architectural key points

3

3.2.1 Sharing NIC nodes

4

3.3 NIC priorities

5

3.4 NIC transfer latency

6

3.5 NIC buffering

7

3.7 Locking NIC

8

3.8 Cache usage

8

Architectural key points

10

4 Dual-core solutions

13

4.1.1 Boot

14

4.1.2 Memory configurations

14

4.1.3 Enabling a second core

14

Figure 5. Dual-core start

15

4.1.4 Sharing peripherals

16

5 Latency measurement

17

Latency measurement

18

6Conclusion

22

7 References

22

References

23

Document Number: AN4947

24

How to Reach Us:

24

Arm AMBA NIC-301 Guía de usuario (54 paginas)

Marca: Arm | Categoria: Redes | Tamaño: 0.49 MB |

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Technical Reference Manual

1

Contents

3

Reference Manual

3

List of Tables

4

List of Figures

5

• About this book on page vii

6

• Feedback on page ix

6

About this book

7

Preface

8

Feedback

9

Chapter 1

10

Introduction

10

ID031010 Non-Confidential

11

1.2 Key features

12

1.4 Product revisions

14

Chapter 2

16

Functional Description

16

2.1 About the functions

17

2.2 Interfaces

18

Combination 1

20

Combination 2

20

Combination 3

20

Combination 4

21

Error response

21

Lock transactions

22

Configuration options

22

2.3 Operation

27

INCR burst type Converted to

29

Aligned INCR4 INCR8

29

Unaligned INCR4 INCR7

29

Aligned INCR9 INCR15 + INCR2

29

FIXED burst type Converted to

30

FIXED1 INCR2

30

FIXED2 INCR2 + INCR2 +

30

Figure 2-2 Remap set to 001

37

Figure 2-3 Remap set to 010

37

101, Slave 1 is removed

38

Chapter 3

39

Programmers Model

39

Type Width

42

Appendix A

48

Revisions

48

Change Location Affects

49

No technical changes -

49

Glossary

50

A 32-bit data item

54

Arm AMBA NIC-301 Especificaciones (178 paginas)

Marca: Arm | Categoria: Redes | Tamaño: 1.61 MB |

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CoreTile

1

Express A15×2 A7×3

1

CoreTile Express A15×2 A7×3

2

CE Declaration of Conformity

3

Contents

4

Appendix B HDLCD controller

5

Appendix D Revisions

5

• About this book on page vii

6

• Feedback on page xi

6

About this book

7

Preface

10

ID062813 Non-Confidential

10

Feedback

11

Chapter 1

12

Introduction

12

1.2 Precautions

15

Chapter 2

16

Hardware Description

16

MBM_nRST

29

Internal resets

32

0x0000_0000

38

2.7 Clocks

39

(CLKF + 1)

46

(CLKOD + 1) (CLKR + 1)x

46

2.8 Interrupts

49

2.8.2 Interrupts

50

2.9 HDLCD

53

2.10 DDR2 memory interface

54

2.11 Debug

55

Components Technical

56

Reference Manual

56

Chapter 3

58

UNPREDICTABLE behavior

59

3.2 Daughterboard memory map

60

You can access NOR 0 at

61

and at

61

0x00_0000_0000

62

3.3 Test chip SCC registers

69

SMC_ADDR_MATCH1_0

75

SMC_ADDR_MASK1_0

75

DMA_BOOT_ADDR

79

DAP ROM Default Target ID

82

DAP ROM Default Instance ID

83

A15_CRNTCLK[3:0]

88

A7_CRNTCLK[3:0]

88

31 16 15 8 0

92

Programmers Model

100

0x000A50F5 to the

108

Cortex-A15_A7 CPU ID

110

0x2A43_0000

119

Reserved

120

0x2A80_0000

126

CNTPL0ACR

136

CNTP_TVAL

139

CNTVL_CVAL

140

Appendix A

147

Signal Descriptions

147

HDRXHDRY

148

TRACE (DUAL) TRACE (SINGLE)

148

Figure A-2 HSB multiplexing

149

A.3 Header connectors

151

Appendix B

155

HDLCD controller

155

B.1 Introduction

156

B.2 HDLCD Programmers Model

157

31 16 15 8 7 0

158

FB_BASE_ADDR

163

FB_LINE_COUNT

164

RESERVED

164

FB_LINE_PITCH

165

31 12 11 0

167

Reserved V_SYNC

167

Reserved V_BACK_PORCH

167

Reserved V_DATA

168

Reserved V_FRONT_PORCH

168

Reserved H_SYNC

169

Reserved H_BACK_PORCH

169

Reserved H_DATA

170

Reserved H_FRONT_PORCH

170

31 30 5432 0

173

BIG_ENDIAN

173

BYTES_PER_PIXEL

173

Appendix C

175

Electrical Specifications

175

C.1 AC characteristics

176

Appendix D

177

Revisions

177

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