ARM AMBA NIC-301 Manual de usuario descargar pdf

Freescale Semiconductor, Inc.

Application Note

Vybrid controller solutions are built on new asymmetrical

multiprocessing architecture using ARM® cores. The

purpose of this application note is to provide some details of

the Vybrid controller solutions system architecture. How an

application is programmed into the Vybrid system-on-chip

(SoC) has a significant impact on application performance,

for instance, in how the application is divided and spread

between cores, how peripherals are set, and which memories

and caches are used. This document is focused on latencies

of memories and cache setting. Several tests are included and

results are presented in tables.

1 Reducing latency

Powerful cores and coprocessors are required for computing

and processing large amounts of data, and high throughput is

mandatory for multimedia applications, but for real-time

control, latency is the most important factor. Latency is the

time delay between cause and effect — for example, the time

between a data request and the receipt of data. Vybrid

solutions are intended for rich applications in real-time and,

to achieve the goal of limited latency, the application must be

programmed in a way that takes into account its architectural

features and restrictions.

Document Number: AN4947

Rev. 0, 07/2014

Contents

1. Reducing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Vybrid architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. Architectural key points . . . . . . . . . . . . . . . . . . . . . . . 3

4. Dual-core solutions . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5. Latency measurement . . . . . . . . . . . . . . . . . . . . . . . . 17

6. Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Understanding Vybrid Architecture

by Jiri Kotzian and Rastislav Pavlanin

1 2 3 4 5 6 ... 23 24

Indice de contenidos

Pagina 1 - 1 Reducing latency

Pagina 2 - 2 Vybrid architecture

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201410 Freescale Semiconductor, Inc.Architectural key pointsto one-way (L2C-310 Techni

Pagina 3 - 3 Architectural key points

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 11Architectural key pointsWe can also use external m

Pagina 4 - 3.2.1 Sharing NIC nodes

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201412 Freescale Semiconductor, Inc.Architectural key pointsMemory aliases were define

Pagina 5 - 3.3 NIC priorities

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 13Dual-core solutions6. Random access: penalty if bl

Pagina 6 - 3.4 NIC transfer latency

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201414 Freescale Semiconductor, Inc.Dual-core solutionsprogramming, the logical core n

Pagina 7 - 3.5 NIC buffering

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 15Dual-core solutionsFigure 5. Dual-core startAn exa

Pagina 8 - 3.8 Cache usage

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201416 Freescale Semiconductor, Inc.Dual-core solutionsFigure 6. Dual-core startNote t

Pagina 9

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 17Latency measurement4.2 Dual-core communication and

Pagina 10 - Architectural key points

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201418 Freescale Semiconductor, Inc.Latency measurementFigure 8. Cortex-M4 latency mea

Pagina 11

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 19Latency measurementNote the following:• TCML (CODE

Pagina 12

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20142 Freescale Semiconductor, Inc.Vybrid architecture2 Vybrid architectureVybrid cont

Pagina 13 - 4 Dual-core solutions

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201420 Freescale Semiconductor, Inc.Latency measurementFigure 9. Cortex-A5 PMCCNTR cod

Pagina 14 - 4.1.3 Enabling a second core

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 21Latency measurementCortex-A5 optimization in the c

Pagina 15 - Figure 5. Dual-core start

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/201422 Freescale Semiconductor, Inc.ConclusionCortex-A5 NOP test results comments:Tabl

Pagina 16 - 4.1.4 Sharing peripherals

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 23References7. [7] Vybrid Security reference manual

Pagina 17 - 5 Latency measurement

Document Number: AN4947Rev. 007/2014Information in this document is provided solely to enable system and software implementers to use Freescale produc

Pagina 18 - Latency measurement

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 3Architectural key points• Internal memories TCM, SR

Pagina 19

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20144 Freescale Semiconductor, Inc.Architectural key points3.2.1 Sharing NIC nodesFigu

Pagina 20

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 5Architectural key pointsis interrupted and M4 is co

Pagina 21

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20146 Freescale Semiconductor, Inc.Architectural key points3.4 NIC transfer latencyThe

Pagina 22 - 7 References

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 7Architectural key pointsLatencies for read/write ar

Pagina 23 - References

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/20148 Freescale Semiconductor, Inc.Architectural key points3.6 Bus width and the trans

Pagina 24 - How to Reach Us:

Understanding Vybrid Architecture, Application Note, Rev. 0, 07/2014Freescale Semiconductor, Inc. 9Architectural key pointsCA5 caches:• Two-way set-as