ARM ARM1176JZF-S Manual de usuario descargar pdf (Pagina 4)

4

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The ARM Register Set

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

User mode

spsr

r13 (sp)

r14 (lr)

IRQ FIQ

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr spsr

r13 (sp)

r14 (lr)

Undef

spsr

r13 (sp)

r14 (lr)

Abort

spsr

r13 (sp)

r14 (lr)

SVC

Current mode Banked out registers

ARM has 37 registers, all 32-bits long

A subset of these registers is accessible

in each mode

888

Program Status Registers

§

Condition code flags

§ N = Negative result from ALU

§ Z = Zero result from ALU

§ C = ALU operation Carried out

§ V = ALU operation oVerflowed

§

Sticky Overflow flag - Q flag

§ Architecture 5TE and later only

§ Indicates if saturation has occurred

§

J bit

§ Architecture 5TEJ and later only

§ J = 1: Processor in Jazelle state

§

Interrupt Disable bits

§ I = 1: Disables IRQ

§ F = 1: Disables FIQ

§

T Bit

§ T = 0: Processor in ARM state

§ T = 1: Processor in Thumb state

§ Introduced in Architecture 4T

§

Mode bits

§ Specify the processor mode

f s x c

2731

N Z C V Q

28 67

I F T mode

1623 15 5 4 024

U n d e f i n e dJ

§

New bits in V6

§

GE[3:0] used by some SIMD

instructions

§

E bit controls load/store endianness

§

A bit disables imprecise data aborts

§

IT [abcde] IF THEN conditional

execution of Thumb2 instruction

groups

10 8919

GE[3:0] E A

IT cond_abc

de

1 2 3 4 5 6 7 8 9 ... 18 19

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