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5.4 SWI handlers
When the SWI handler is entered, it must establish which SWI is being called. This information can be stored in bits
0-23 of the instruction itself, as shown in Figure 5-1, or passed in an integer register, usually one of r0-r3.
Figure 5-1 ARM SWI instruction
The top-level SWI handler can load the SWI instruction relative to the link register (LDR swi, [lr, #-4]). Do this
in assembly language, or C/C++ inline assembler.
The handler must first load the SWI instruction that caused the exception into a register. At this point, lr_SVC holds
the address of the instruction that follows the SWI instruction, so the SWI is loaded into the register (in this case r0)
using:
LDR r0, [lr,#-4]
The handler can then examine the comment field bits, to determine the required operation. The SWI number is
extracted by clearing the top eight bits of the opcode:
BIC r0, r0, #0xFF000000
Example 5-5 shows how you can put these instructions together to form a top-level SWI handler.
See Determining the processor state for an example of a handler that deals with both ARM-state and Thumb-state
SWI instructions.
Example 5-5
AREA TopLevelSwi, CODE, READONLY ; Name this block of code.
EXPORT SWI_Handler
SWI_Handler
STMFD sp!,{r0-r12,lr} ; Store registers.
LDR r0,[lr,#-4] ; Calculate address of SWI instruction and load it into r
0.
BIC r0,r0,#0xff000000 ; Mask off top 8 bits of instruction to give SWI number.
;
; Use value in r0 to determine which SWI routine to execute.
;
LDMFD sp!, {r0-r12,pc}^ ; Restore registers and return.
END ; Mark end of this file.
5.4.1 SWI handlers in assembly language
The easiest way to call the handler for the requested SWI number is to use a jump table. If r0 contains the SWI
number, the code in Example 5-6 can be inserted into the top-level handler given in Example 5-5, following on from
the BIC instruction.
Example 5-6 SWI jump table
CMP r0,#MaxSWI ; Range check
LDRLS pc, [pc,r0,LSL #2]
B SWIOutOfRange
SWIJumpTable
DCD SWInum0
DCD SWInum1
; DCD for each of other SWI routines
SWInum0 ; SWI number 0 code
B EndofSWI
SWInum1 ; SWI number 1 code
B EndofSWI
; Rest of SWI handling code
;
EndofSWI
; Return execution to top level
; SWI handler so as to restore
; registers and return to program.
Handling Processor Exceptions
Copyright ?1999 2001 ARM Limited 5-8
- ARM® Developer Suite 1
- Version 1.2 1
- Developer Guide 1
- About this book 2
- ARM publications 3
- Other publications 3
- Feedback 4
- 1 Introduction 5
- Introduction 6
- 1.3 Developing for the ARM 7
- 1.3.5 Writing Code for ROM 8
- 2.1.1 ATPCS variants 9
- 2.1.2 ARM C libraries 9
- • Read-only memory 10
- 2.2 Register roles and names 11
- 2.3 The stack 12
- 2.4 Parameter passing 14
- 2.5 Stack limit checking 15
- 2.6.2 Writing code for ROPI 17
- 2.7.1 Reentrant routines 18
- 2.9 Floating-point options 20
- 3 Interworking ARM and Thumb 22
- 3.1 About interworking 22
- Interworking ARM and Thumb 23
- 3.2.3 Example ARM header 24
- Building the example 25
- 3.2.4 ARM architecture v5T 25
- 3.2.5 Labels in Thumb code 26
- C interworking example 27
- 5. Type go to run the code 31
- String copying example 33
- Operand expressions 33
- Physical registers 33
- 4.1.4 Usage 35
- 4.1.5 Examples 36
- Dot product 37
- Long multiplies 37
- • LDRB/STRB for char 39
- • LDR/STR for int 39
- C++ calling conventions 42
- C++ data types 42
- Symbol name mangling 43
- 4.4.3 Examples 43
- Calling C from C++ 44
- Calling C++ from C 45
- Handling Processor Exceptions 48
- • the address of the handler 53
- 5.4 SWI handlers 55
- Nested SWIs in C and C++ 57
- 5.5 Interrupt handlers 61
- • Single-channel DMA transfer 63
- • Dual-channel DMA transfer 63
- • Interrupt prioritization 63
- • Context switch 63
- Interrupt prioritization 64
- Context switch 65
- 5.6 Reset handlers 67
- 5.8 Prefetch Abort handler 69
- 5.9 Data Abort handler 70
- • A single extended handler 71
- • Several chained handlers 71
- Handling the exception 72
- 5.11.2 The return address 72
- FIQ and IRQ handlers 73
- Prefetch Abort handlers 73
- Data Abort handlers 73
- 5.12 System mode 75
- 6 Writing Code for ROM 76
- 6.2.1 ROM at 0x0 77
- 6.2.2 RAM at 0x0 77
- Implementing RAM at 0x0 77
- System decoder 78
- 6.3 Initializing the system 79
- 6.4.1 Memory map 81
- 6.4.2 Sample code 82
- • five execution regions: 83
- 6.5.3 Sample code 84
- 6.5.4 Building the example 88
- Using the CodeWarrior IDE 89
- Using the command line 89
- 6.6.1 Memory map 90
- 6.6.3 Initialization code 91
- 6.6.4 Building the example 91
- 6.7.1 Memory map 93
- 6.7.2 Building the example 93
- 6.7.3 Sample code 93
- 6.8.1 Memory map 97
- 6.8.2 Building the example 97
- 6.8.4 Sample code 98
- 6.9.2 Using unions 100
- Using an array of shorts 100
- Using a struct 100
- 6.9.4 Using scatter loading 101
- 6.9.5 Code efficiency 102
- 6.10 Troubleshooting 103
- Writing Code for ROM 104
- Code (or read-only) segments 105
- Data (or read-write) segments 105
- Debug data 105
- 7.1.1 About caches 106
- ARMulator Pagetable model 106
- 7.1.4 Cache performance 107
- 7.3 Memory protection units 109
- 7.4 Configuring a PU 110
- 7.5 Memory management units 113
- 7.6 Configuring an MMU 115
- 7.7 Tightly coupled memory 117
- 7.7.3 ARM966E-S warm reset 118
- Debug Communications Channel 120
- 8.4 Target transfer of data 123
- • Using armsd 125
- • Using AXD 125
- Issuing commands 126
- Using AXD 126
- 8.7 Access from Thumb state 129
- 8.8 Semihosting 130
- Glossary 131
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