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The following sections give a summary of the values to which the processor sets lr_mode if an exception occurs
when the processor is in Thumb state.
SWI and Undefined Instruction handlers
The handler's return instruction (MOVS pc,lr) changes the program counter to the address of the next instruction to
execute. This is at (pc − 2), so the value stored by the processor in lr_mode is (pc − 2).
FIQ and IRQ handlers
The handler's return instruction (SUBS pc,lr,#4) changes the program counter to the address of the next
instruction to execute. Because the program counter is updated before the exception is taken, the next instruction is
at (pc − 4). The value stored by the processor in lr_mode is therefore pc.
Prefetch Abort handlers
The handler's return instruction (SUBS pc,lr,#4) changes the program counter to the address of the aborted
instruction. Because the program counter is not updated before the exception is taken, the aborted instruction is at
(pc − 4). The value stored by the processor in lr_mode is therefore pc.
Data Abort handlers
The handler's return instruction (SUBS pc,lr,#8) changes the program counter to the address of the aborted
instruction. Because the program counter is updated before the exception is taken, the aborted instruction is at (pc −
6). The value stored by the processor in lr_mode is therefore (pc + 2).
5.11.3 Determining the processor state
An exception handler may need to determine whether the processor was in ARM or Thumb state when the exception
occurred. SWI handlers, especially, might need to read the processor state. This is done by examining the SPSR
T-bit. This bit is set for Thumb state and clear for ARM state.
Both ARM and Thumb instruction sets have the SWI instruction. When calling SWIs from Thumb state, you must
consider three things:
• the address of the instruction is at (lr − 2), rather than (lr − 4)
• the instruction itself is 16-bit, and so requires a halfword load (see Figure 5-5)
• the SWI number is held in 8 bits instead of the 24 bits in ARM state.
Figure 5-5 Thumb SWI instruction
Example 5-19 shows ARM code that handles a SWI from both sources. Consider the following points:
• Each of the do_swi_x routines could carry out a switch to Thumb state and back again to improve code density
if required.
• You can replace the jump table by a call to a C function containing a switch() statement to implement the
SWIs.
• It is possible for a SWI number to be handled differently depending upon the state it is called from.
• The range of SWI numbers accessible from Thumb state can be increased by calling SWIs dynamically (as
described in SWI handlers).
Example 5-19
T_bit EQU 0x20 ; Thumb bit of CPSR/SPSR, that is, bit 5.
:
:
SWIHandler
STMFD sp!, {r0-r3,r12,lr} ; Store registers.
MRS r0, spsr ; Move SPSR into general purpose register.
TST r0, #T_bit ; Occurred in Thumb state?
LDRNEH r0,[lr,#-2] ; Yes: load halfword and...
BICNE r0,r0,#0xFF00 ; ...extract comment field.
LDREQ r0,[lr,#-4] ; No: load word and...
BICEQ r0,r0,#0xFF000000 ; ...extract comment field.
Handling Processor Exceptions
Copyright ?1999 2001 ARM Limited 5-26
- ARM® Developer Suite 1
- Version 1.2 1
- Developer Guide 1
- About this book 2
- ARM publications 3
- Other publications 3
- Feedback 4
- 1 Introduction 5
- Introduction 6
- 1.3 Developing for the ARM 7
- 1.3.5 Writing Code for ROM 8
- 2.1.1 ATPCS variants 9
- 2.1.2 ARM C libraries 9
- • Read-only memory 10
- 2.2 Register roles and names 11
- 2.3 The stack 12
- 2.4 Parameter passing 14
- 2.5 Stack limit checking 15
- 2.6.2 Writing code for ROPI 17
- 2.7.1 Reentrant routines 18
- 2.9 Floating-point options 20
- 3 Interworking ARM and Thumb 22
- 3.1 About interworking 22
- Interworking ARM and Thumb 23
- 3.2.3 Example ARM header 24
- Building the example 25
- 3.2.4 ARM architecture v5T 25
- 3.2.5 Labels in Thumb code 26
- C interworking example 27
- 5. Type go to run the code 31
- String copying example 33
- Operand expressions 33
- Physical registers 33
- 4.1.4 Usage 35
- 4.1.5 Examples 36
- Dot product 37
- Long multiplies 37
- • LDRB/STRB for char 39
- • LDR/STR for int 39
- C++ calling conventions 42
- C++ data types 42
- Symbol name mangling 43
- 4.4.3 Examples 43
- Calling C from C++ 44
- Calling C++ from C 45
- Handling Processor Exceptions 48
- • the address of the handler 53
- 5.4 SWI handlers 55
- Nested SWIs in C and C++ 57
- 5.5 Interrupt handlers 61
- • Single-channel DMA transfer 63
- • Dual-channel DMA transfer 63
- • Interrupt prioritization 63
- • Context switch 63
- Interrupt prioritization 64
- Context switch 65
- 5.6 Reset handlers 67
- 5.8 Prefetch Abort handler 69
- 5.9 Data Abort handler 70
- • A single extended handler 71
- • Several chained handlers 71
- Handling the exception 72
- 5.11.2 The return address 72
- FIQ and IRQ handlers 73
- Prefetch Abort handlers 73
- Data Abort handlers 73
- 5.12 System mode 75
- 6 Writing Code for ROM 76
- 6.2.1 ROM at 0x0 77
- 6.2.2 RAM at 0x0 77
- Implementing RAM at 0x0 77
- System decoder 78
- 6.3 Initializing the system 79
- 6.4.1 Memory map 81
- 6.4.2 Sample code 82
- • five execution regions: 83
- 6.5.3 Sample code 84
- 6.5.4 Building the example 88
- Using the CodeWarrior IDE 89
- Using the command line 89
- 6.6.1 Memory map 90
- 6.6.3 Initialization code 91
- 6.6.4 Building the example 91
- 6.7.1 Memory map 93
- 6.7.2 Building the example 93
- 6.7.3 Sample code 93
- 6.8.1 Memory map 97
- 6.8.2 Building the example 97
- 6.8.4 Sample code 98
- 6.9.2 Using unions 100
- Using an array of shorts 100
- Using a struct 100
- 6.9.4 Using scatter loading 101
- 6.9.5 Code efficiency 102
- 6.10 Troubleshooting 103
- Writing Code for ROM 104
- Code (or read-only) segments 105
- Data (or read-write) segments 105
- Debug data 105
- 7.1.1 About caches 106
- ARMulator Pagetable model 106
- 7.1.4 Cache performance 107
- 7.3 Memory protection units 109
- 7.4 Configuring a PU 110
- 7.5 Memory management units 113
- 7.6 Configuring an MMU 115
- 7.7 Tightly coupled memory 117
- 7.7.3 ARM966E-S warm reset 118
- Debug Communications Channel 120
- 8.4 Target transfer of data 123
- • Using armsd 125
- • Using AXD 125
- Issuing commands 126
- Using AXD 126
- 8.7 Access from Thumb state 129
- 8.8 Semihosting 130
- Glossary 131
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