ARM VERSION 1.2 Ficha de datos descargar pdf (Pagina 144)

Semihosting

5.2.4 Multi-ICE

When using Multi-ICE in default configuration, semihosting is implemented as follows:

1. On ARM7 processors:

a. A breakpoint is set on the SWI vector.

b. When this breakpoint is hit, Multi-ICE examines the SWI number.

c. If the SWI is recognized as a semihosting SWI, Multi-ICE emulates it and

transparently restarts execution of the application.

If the SWI is not recognized as a semihosting SWI, Multi-ICE halts the

processor and reports an error.

2. On other processors:

a. Vector-catch logic traps SWIs.

b. If the SWI is recognized as a semihosting SWI, Multi-ICE emulates it and

transparently restarts execution of the application.

If the SWI is not recognized as a semihosting SWI, Multi-ICE halts the

processor and reports an error.

This semihosting mechanism can be disabled or changed by the following debugger

internal variables:

$semihosting_enabled

Set this variable to 0 to disable semihosting. If you are debugging an

application running from ROM, this allows you to use an additional

watchpoint unit.

Set this variable to 1 to enable semihosting. This is the default.

Set this variable to 2 to enable Debug Communications Channel

semihosting.

The S bit in

$vector_catch

has no effect unless semihosting is disabled.

$semihosting_vector

This variable controls the location of the breakpoint set by Multi-ICE to

detect a semihosted SWI. It is set to the SWI entry in the exception vector

table (

0x8

) by default.

If your application requires semihosting as well as having its own SWI

handler, set

$semihosting_vector

to an address in your SWI handler. This

address must point to an instruction that is only executed if your SWI

handler has identified a call to a semihosting SWI. All registers must

already have been restored to whatever values they had on entry to your

SWI handler.

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ARM VERSION 1.2 Ficha de datos Pagina 144