ARM Cortex-M3 Guía de usuario descargar pdf (Pagina 37)

Programmers Model

ID072410 Non-Confidential

Push Push

PUSH {<reglist>}

1 + N

Push with link register

PUSH {<reglist>, LR}

1 + N

Pop Pop

POP {<reglist>}

1 + N

Pop and return

POP {<reglist>, PC}

1 + N + P

Semaphore Load exclusive

LDREX Rd, [Rn, #<imm>]

Load exclusive half

LDREXH Rd, [Rn]

Load exclusive byte

LDREXB Rd, [Rn]

Store exclusive

STREX Rd, Rt, [Rn, #<imm>]

Store exclusive half

STREXH Rd, Rt, [Rn]

Store exclusive byte

STREXB Rd, Rt, [Rn]

Clear exclusive monitor

CLREX

Branch Conditional

B<cc> <label>

1 or 1 + P

Unconditional

B <label>

1 + P

With link

BL <label>

1 + P

With exchange

BX Rm

1 + P

With link and exchange

BLX Rm

1 + P

Branch if zero

CBZ Rn, <label>

1 or 1 + P

Branch if non-zero

CBNZ Rn, <label>

1 or 1 + P

Byte table branch

TBB [Rn, Rm]

2 + P

Halfword table branch

TBH [Rn, Rm, LSL#1]

2 + P

State change Supervisor call

SVC #<imm>

If-then-else

IT... <cond>

Disable interrupts

CPSID <flags>

1 or 2

Enable interrupts

CPSIE <flags>

1 or 2

Read special register

MRS Rd, <specreg>

1 or 2

Write special register

MSR <specreg>, Rn

1 or 2

Breakpoint

BKPT #<imm>

Extend Signed halfword to word

SXTH Rd, <op2>

Signed byte to word

SXTB Rd, <op2>

Unsigned halfword

UXTH Rd, <op2>

Unsigned byte

UXTB Rd, <op2>

Table 3-1 Cortex-M3 instruction set summary (continued)

Operation Description Assembler Cycles

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 136 137

Comentarios a estos manuales

Sin comentarios

ARM Cortex-M3 Guía de usuario Pagina 37

Comentarios a estos manuales

Relacionado con productos y manuales para Procesadores ARM Cortex-M3