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Embedded Trace Macrocell

ID072410 Non-Confidential

[6:4] Port size [2:0] The ETM-M3 has no influence over the external pins used for trace. These bits are implemented

but not used.

On an ETM reset these bits reset to

0b001

[3:1] - Reserved

[0] ETM power down This bit can be used by an implementation to control if the ETM is in a low power state. This bit

must be cleared by the trace software tools at the beginning of a debug session.

When this bit is set to 1, writes to some registers and fields might be ignored. You can always write

to the following registers and fields:

• ETMCR bit [0]

•ETMLAR

• ETMCLAIMSET register

• ETMCLAIMCLR register.

When the ETMCR is written with this bit set to 1, bits other than bit [0] might be ignored.

On an ETM reset this bit is set to 1.

Table 10-7 ETMCR bit assignments (continued)

Bits Name Function

1 2 ... 94 95 96 97 98 99 100 101 102 103 104 ... 136 137

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ARM Cortex-M3 Guía de usuario Pagina 99