ARM Cortex-M3 Guía de usuario descargar pdf (Pagina 44)

Programmers Model

ID072410 Non-Confidential

3.5 Write buffer

To prevent bus wait cycles from stalling the processor during data stores, buffered stores to the

DCode and System buses go through a one-entry write buffer. If the write buffer is full,

subsequent accesses to the bus stall until the write buffer has drained. The write buffer is only

used if the bus waits the data phase of the buffered store, otherwise the transaction completes

on the bus.

DMB

and

DSB

instructions wait for the write buffer to drain before completing. If an interrupt

comes in while

DMB

DSB

is waiting for the write buffer to drain, the processor returns to the

instruction following the

DMB

DSB

after the interrupt completes. This is because interrupt

processing acts as a memory barrier operation.

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 136 137

Sin comentarios

ARM Cortex-M3 Guía de usuario Pagina 44