ARM Cortex r1p3 Ficha de datos

February 2014 DocID024647 Rev 1 1/138RM0352Reference manualBrain smart hub familyIntroductionThis reference manual targets application developers. It

List of figures RM035210/138 DocID024647 Rev 1List of figuresFigure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SPI (serial peripheral interface) RM0352100/138 DocID024647 Rev 111 SPI (serial peripheral interface)The SPI block is an IP provided by ARM (PL022 “P

DocID024647 Rev 1 101/138RM0352 SPI (serial peripheral interface)13711.3 SPI registersThe SPI has following programmable parameters:• Master or slave

SPI (serial peripheral interface) RM0352102/138 DocID024647 Rev 111.4 SPI register descriptionsThis section describes the PrimeCell SSP registers. Ta

DocID024647 Rev 1 103/138RM0352 SPI (serial peripheral interface)137[5:4] FRF Frame format:00: Motorola SPI frame format01: TI synchronous serial fram

SPI (serial peripheral interface) RM0352104/138 DocID024647 Rev 111.4.2 Control register 1, SSPCR1The SSPCR1 register characteristics are:Purpose The

DocID024647 Rev 1 105/138RM0352 SPI (serial peripheral interface)137When the SSPDR is written to, the entry in the transmit FIFO, pointed to by the wr

SPI (serial peripheral interface) RM0352106/138 DocID024647 Rev 1Table 100 shows the bit assignments. 11.4.5 Clock prescale register, SSPCPSR

DocID024647 Rev 1 107/138RM0352 SPI (serial peripheral interface)137Table 101 shows the bit assignments. 11.4.6 Interrupt mask set or clear r

SPI (serial peripheral interface) RM0352108/138 DocID024647 Rev 111.4.7 Raw interrupt status register, SSPRISThe SSPRIS register characteristics are:

DocID024647 Rev 1 109/138RM0352 SPI (serial peripheral interface)13711.4.9 Interrupt clear register, SSPICRThe SSPICR register characteristics are:Pu

DocID024647 Rev 1 11/138RM0352 Referenced document1371 Referenced documentTable 1. Referenced documentReference number Name Owner RevisionDUI0497A_cor

SPI (serial peripheral interface) RM0352110/138 DocID024647 Rev 1The following subsections describe the four 8-bit peripheral identification registers

DocID024647 Rev 1 111/138RM0352 SPI (serial peripheral interface)137Usage constraints There are no usage constraints. Configurations Available in a

SPI (serial peripheral interface) RM0352112/138 DocID024647 Rev 1The following subsections describe the four, 8-bit PrimeCell identification registers

DocID024647 Rev 1 113/138RM0352 SPI (serial peripheral interface)137Configurations Available in all SSP configurations. Attributes See Table 96 on pag

SPI (serial peripheral interface) RM0352114/138 DocID024647 Rev 1Provision of the individual outputs in addition to a combined interrupt output, enabl

DocID024647 Rev 1 115/138RM0352 UART (universal asynchronous receive transmit)13712 UART (universal asynchronous receive transmit)The Brain device ha

UART (universal asynchronous receive transmit) RM0352116/138 DocID024647 Rev 112.2 IrDA SIR blockThe IrDA “Serial InfraRed” (SIR) block contains an I

DocID024647 Rev 1 117/138RM0352 UART (universal asynchronous receive transmit)137The transmit and receive data flow interrupts UARTRXINTR and UARTTXIN

UART (universal asynchronous receive transmit) RM0352118/138 DocID024647 Rev 1To update the transmit FIFO you must:• Write data to the transmit FIFO,

DocID024647 Rev 1 119/138RM0352 UART (universal asynchronous receive transmit)137 Table 114. UART register summaryOffset Name Type Reset Width

System and memory overview RM035212/138 DocID024647 Rev 12 System and memory overview2.1 System architectureThe main system consists of:• One master:

UART (universal asynchronous receive transmit) RM0352120/138 DocID024647 Rev 112.6 Register descriptionsThis section describes the UART registers. Tab

DocID024647 Rev 1 121/138RM0352 UART (universal asynchronous receive transmit)137 12.6.2 Receive status register / error clear register, UART

UART (universal asynchronous receive transmit) RM0352122/138 DocID024647 Rev 112.6.3 Flag register, UARTFRThe UARTFR register is the flag register. Af

DocID024647 Rev 1 123/138RM0352 UART (universal asynchronous receive transmit)13712.6.4 IrDA low-power counter register, UARTILPRThe UARTILPR registe

UART (universal asynchronous receive transmit) RM0352124/138 DocID024647 Rev 112.6.5 Integer baud rate register, UARTIBRDThe UARTIBRD register is the

DocID024647 Rev 1 125/138RM0352 UART (universal asynchronous receive transmit)137The maximum error using a 6-bit UARTFBRD register = 1/64 × 100 = 1.56

UART (universal asynchronous receive transmit) RM0352126/138 DocID024647 Rev 112.6.7 Line control register, UARTLCR_HThe UARTLCR_H register is the li

DocID024647 Rev 1 127/138RM0352 UART (universal asynchronous receive transmit)137Note: To update the three registers there are two possible sequences:

UART (universal asynchronous receive transmit) RM0352128/138 DocID024647 Rev 1Note: To enable transmission, the TXE bit and UARTEN bit must be set to

DocID024647 Rev 1 129/138RM0352 UART (universal asynchronous receive transmit)137Program the control registers as follows:1. Disable the UART.2. Wait

DocID024647 Rev 1 13/138RM0352 System and memory overview1372.2 Memory organizationIntroductionProgram memory, data memory, registers and I/O ports ar

UART (universal asynchronous receive transmit) RM0352130/138 DocID024647 Rev 112.6.10 Interrupt mask set/clear register, UARTIMSCThe UARTIMSC registe

DocID024647 Rev 1 131/138RM0352 UART (universal asynchronous receive transmit)13712.6.11 Raw interrupt status register, UARTRISThe UARTRIS register i

UART (universal asynchronous receive transmit) RM0352132/138 DocID024647 Rev 112.6.12 Masked interrupt status register, UARTMISThe UARTMIS register i

DocID024647 Rev 1 133/138RM0352 UART (universal asynchronous receive transmit)13712.6.13 Interrupt clear register, UARTICRThe UARTICR register is the

UART (universal asynchronous receive transmit) RM0352134/138 DocID024647 Rev 1UARTPeriphID0 registerThe UARTPeriphID0 register is hard coded and the f

DocID024647 Rev 1 135/138RM0352 UART (universal asynchronous receive transmit)137UARTPeriphID3 registerThe UARTPeriphID3 register is hard coded and th

UART (universal asynchronous receive transmit) RM0352136/138 DocID024647 Rev 1UARTPCellID2 registerThe UARTPCellID2 register is hard coded and the fie

DocID024647 Rev 1 137/138RM0352 Revision history13713 Revision history Table 139. Document revision historyDate Revision Changes06-Feb-2014 1

RM0352138/138 DocID024647 Rev 1 Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroe

System and memory overview RM035214/138 DocID024647 Rev 1 Table 2. Memory tableAddressCortex-M0 address mapSize Remap = 0 Remap = 10x0000_0000

DocID024647 Rev 1 15/138RM0352 System and memory overview1372.3 Embedded SRAMThe Brain device features up to 128 KBytes of static SRAM (RAM bank0 + RA

System and memory overview RM035216/138 DocID024647 Rev 12.5 Physical remapThe application software can switch between two memory mappings (see Table

DocID024647 Rev 1 17/138RM0352 Interrupts1373 InterruptsInterrupts are handled by the Cortex-M0 “Nested Vector Interrupt controller” (NVIC). The NVIC

Interrupts RM035218/138 DocID024647 Rev 116 Init 0 Settable TIMER2A Dual Timer2A 0x0000_0080 17 Init 0 Settable TIMER2B Dual Timer2B 0x000

DocID024647 Rev 1 19/138RM0352 GPIO1374 GPIOThe Brain device proposes 11 programmable I/Os.Each GPIO provides one programmable input or output that ca

Contents RM03522/138 DocID024647 Rev 1Contents1 Referenced document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

GPIO RM035220/138 DocID024647 Rev 1 Table 5. GPIO configuration registersAddress Bit Field name Reset R/W Description0x00 14 GPIO_WDA

DocID024647 Rev 1 21/138RM0352 Clock and reset management unit1375 Clock and reset management unit5.1 IntroductionThe Brain CRMU implements the clock

Clock and reset management unit RM035222/138 DocID024647 Rev 1Figure 2. Clock generationFONBLQFONBLQVHOFONBLQFONBLQVHOFONBLQFONBLQFORFNBVZLWFKFO

DocID024647 Rev 1 23/138RM0352 Clock and reset management unit1375.2.2 RC 80 MHz clockThe 80 MHz clock is generated by an on-chip RC oscillator and i

Clock and reset management unit RM035224/138 DocID024647 Rev 15.2.10 SysTick clockThe SysTick timer is clocked on the processor clock. 5.2.11 SPI cloc

DocID024647 Rev 1 25/138RM0352 Clock and reset management unit137Figure 3. Reset generation5.3.2 Power-on resetThe power-on reset signal is the combin

Clock and reset management unit RM035226/138 DocID024647 Rev 15.3.5 System reset requestThe system reset request is generated by the debug circuitry

DocID024647 Rev 1 27/138RM0352 Clock and reset management unit1375.4 CRMU registersThe CRMU registers are listed in Table 7 on page 27 and are describ

Clock and reset management unit RM035228/138 DocID024647 Rev 1 1. The field PROC_CLK_SEL is programmed to select the clock output from the 4-w

DocID024647 Rev 1 29/138RM0352 Clock and reset management unit1372. The field HS_OSC_SEL is programmed to select the clock output from the 3-way cloc

DocID024647 Rev 1 3/138RM0352 Contents65.3.6 Lockup reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock and reset management unit RM035230/138 DocID024647 Rev 1 Table 15. CRMU_ECCR0(1)Address Bit Field name Reset R/W DescriptionCRM

DocID024647 Rev 1 31/138RM0352 Embedded Flash memory1376 Embedded Flash memory6.1 DescriptionThe Flash array consists of 64 kBytes or 16 kWords (1638

Embedded Flash memory RM035232/138 DocID024647 Rev 1 6.3 Flash controller registers6.3.1 Interrupt registersThe interrupt status, raw status

DocID024647 Rev 1 33/138RM0352 Embedded Flash memory137The CMDDONE and CMDSTART bits are updated a few clock cycles after the requested command has be

Embedded Flash memory RM035234/138 DocID024647 Rev 16.3.4 Command registerStatus bits:• Writing to the COMMAND register will start the action that wil

DocID024647 Rev 1 35/138RM0352 Embedded Flash memory137The APB actions that need to be performed are:• Write ADDRESS register value of the word you wa

Embedded Flash memory RM035236/138 DocID024647 Rev 1 6.3.6 Unlock registersThe unlock registers UNLOCKM and UNLOCKL form together the special

DocID024647 Rev 1 37/138RM0352 Embedded Flash memory137Figure 4. Flash wrapper state machine operation6.5 Flash protection (ready state)After the rec

Watchdog timer (WDG) RM035238/138 DocID024647 Rev 17 Watchdog timer (WDG)The watchdog timer (WDG aka WDT) provides a way of recovering from software

DocID024647 Rev 1 39/138RM0352 Watchdog timer (WDG)137disabled the watchdog counter is also stopped, and when the interrupt is enabled the counter wil

Contents RM03524/138 DocID024647 Rev 18.2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488.

Watchdog timer (WDG) RM035240/138 DocID024647 Rev 1WDG base + 0xFEC WDTPeriphID3Peripheral identification register bits 31:24. See Section 7.2.8: Watc

DocID024647 Rev 1 41/138RM0352 Watchdog timer (WDG)1377.2.1 Watchdog load register (WDT_LR)The WDT_LR register is a 32-bit register containing the va

Watchdog timer (WDG) RM035242/138 DocID024647 Rev 17.2.3 Watchdog control register WDT_CRThe WDT_CR register allows configuring the watchdog timer. T

DocID024647 Rev 1 43/138RM0352 Watchdog timer (WDG)1377.2.5 Watchdog raw interrupt status register WDT_RISThe WDTRIS register is the raw interrupt st

Watchdog timer (WDG) RM035244/138 DocID024647 Rev 17.2.7 Watchdog lock register WDT_LOCKUse of this register allows write access to all other registe

DocID024647 Rev 1 45/138RM0352 Watchdog timer (WDG)137Table 42. Watchdog peripheral identification register WDTPeriphID0-3 - part 2 Table 43.

Watchdog timer (WDG) RM035246/138 DocID024647 Rev 1Table 47. Watchdog PCell identification register WDTPCellID0-3 - part 2 Table 48. Watchdog

DocID024647 Rev 1 47/138RM0352 ARM© dual timer module (SP804)1378 ARM© dual timer module (SP804)This section is intended for hardware and software eng

ARM© dual timer module (SP804) RM035248/138 DocID024647 Rev 1Figure 5 shows a simplified block diagram of the module.Figure 5. Simplified block diagra

DocID024647 Rev 1 49/138RM0352 ARM© dual timer module (SP804)137The dual timer module consists of two identical programmable “Free Running Counters” (

DocID024647 Rev 1 5/138RM0352 Contents610.2.17 SMBUS slave control register (I2C_SMB_SCR) . . . . . . . . . . . . . . . . . . 9510.2.18 I2C periphera

ARM© dual timer module (SP804) RM035250/138 DocID024647 Rev 18.2.2 Functional descriptionThe dual timer module block diagram is shown in Figure 6.Figu

DocID024647 Rev 1 51/138RM0352 ARM© dual timer module (SP804)137Free running counter blocksThe two FRCs are identical and contain the 32/16-bit down c

ARM© dual timer module (SP804) RM035252/138 DocID024647 Rev 1TIMCLK equals PCLK and TIMCLKENX equals oneFigure 7 shows the case where TIMCLK is identi

DocID024647 Rev 1 53/138RM0352 ARM© dual timer module (SP804)137Figure 9 shows how the timer clock enable is generated by the prescaler.Figure 9. Pres

ARM© dual timer module (SP804) RM035254/138 DocID024647 Rev 1Free running modeFree running mode is selected by setting the following bits in the Timer

DocID024647 Rev 1 55/138RM0352 ARM© dual timer module (SP804)137new load value and uses this new load value for each subsequent reload for as long as

ARM© dual timer module (SP804) RM035256/138 DocID024647 Rev 1Figure 11 illustrates an example of the timing for an interrupt being raised and cleared.

DocID024647 Rev 1 57/138RM0352 ARM© dual timer module (SP804)137 For example, the TimerXLoad value required for a 1 ms periodic interval with

ARM© dual timer module (SP804) RM035258/138 DocID024647 Rev 18.3.1 Summary of registersA summary of the registers is provided in Table 52 and base ad

DocID024647 Rev 1 59/138RM0352 ARM© dual timer module (SP804)1378.3.2 Register descriptionsThis section describes the dual timer module registers:• Lo

Contents RM03526/138 DocID024647 Rev 112.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ARM© dual timer module (SP804) RM035260/138 DocID024647 Rev 1Load register, TimerXLoadThe TimerXLoad register is a 32-bit register that contains the v

DocID024647 Rev 1 61/138RM0352 ARM© dual timer module (SP804)137Control register, TimerXControlThe bit assignments of the control register are listed

ARM© dual timer module (SP804) RM035262/138 DocID024647 Rev 1Raw interrupt status register, TimerXRISThe TimerXRIS register indicates the raw interrup

DocID024647 Rev 1 63/138RM0352 ARM© dual timer module (SP804)137Figure 13 shows the bit assignments for the registers.Figure 13. Peripheral identifica

ARM© dual timer module (SP804) RM035264/138 DocID024647 Rev 1Timer peripheral ID1 register, TimerPeriphID1The TimerPeriphID1 register is hard-coded an

DocID024647 Rev 1 65/138RM0352 ARM© dual timer module (SP804)137Figure 14. PrimeCell identification register bit assignmentsThe four, 8-bit PrimeCell

ARM© dual timer module (SP804) RM035266/138 DocID024647 Rev 1PrimeCell ID2 register, TimerPCellID2The TimerPCellID2 register is hard-coded and the fie

DocID024647 Rev 1 67/138RM0352 System timer (SysTick)1379 System timer (SysTick)9.1 About the SysTickThe Brain device also includes a system timer (S

System timer (SysTick) RM035268/138 DocID024647 Rev 19.3 SysTick registers descriptions9.3.1 SysTick control and status register (SYST_CSR)Address:

DocID024647 Rev 1 69/138RM0352 System timer (SysTick)137Type: R/WReset: Description: SysTick reload value registerTo generate a multi-shot timer with

DocID024647 Rev 1 7/138RM0352 List of tables9List of tablesTable 1. Referenced document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

System timer (SysTick) RM035270/138 DocID024647 Rev 1Reset: 0x80000000Description: SysTick calibration value register9.4 Configuring SysTickTo configu

DocID024647 Rev 1 71/138RM0352 I2C bus interface13710 I2C bus interfaceThe Brain device provides two I2C bus interfaces that support following feature

I2C bus interface RM035272/138 DocID024647 Rev 1I2C Base +0x034 I2C_MISRI2C masked interrupt status register. See Section 10.2.12: I2C masked interrup

DocID024647 Rev 1 73/138RM0352 I2C bus interface13710.2 I2C register descriptions10.2.1 I2C control register (I2C_CR) Table 71. I2C control re

I2C bus interface RM035274/138 DocID024647 Rev 1[25:20] FREQ: internal clock frequency (SMBUS)This field must be programmed to generate correct timin

DocID024647 Rev 1 75/138RM0352 I2C bus interface137 [9] RESERVEDFRX flushes the receive circuitry (FIFO, fsm). The configuration of the I2C node (regi

I2C bus interface RM035276/138 DocID024647 Rev 1[2:1] OM: Operating Mode.00: Slave mode. The peripheral can only respond (transmit/receive) when addre

DocID024647 Rev 1 77/138RM0352 I2C bus interface13710.2.2 I2C slave control register (I2C_SCR) Table 72. I2C slave control register (I2C_SCR)A

I2C bus interface RM035278/138 DocID024647 Rev 1Description: The control code word defines the features of the transfer. A typical transfer is defined

DocID024647 Rev 1 79/138RM0352 I2C bus interface13710.2.4 I2C transmit FIFO register (I2C_TFR) Table 74. I2C transmit FIFO register (I2C_TFR)A

List of tables RM03528/138 DocID024647 Rev 1Table 49. Watchdog PCell identification register WDTPCellID0-3 - part 4 . . . . . . . . . . . . . . . . .

I2C bus interface RM035280/138 DocID024647 Rev 110.2.5 I2C status register (I2C_SR)Table 75. I2C status register (I2C_SR)Address: I2CBaseAddress + 0x

DocID024647 Rev 1 81/138RM0352 I2C bus interface137[20] SMBDEFAULT: SMBus device default address (slave mode)0: no SMBus device default address1: SMBu

I2C bus interface RM035282/138 DocID024647 Rev 1[3:2] STATUS: controller status. Valid for the operations MW, MR, WTS, RFS.0: NOP: no operation is in

DocID024647 Rev 1 83/138RM0352 I2C bus interface13710.2.6 I2C receive FIFO register (I2C_RFR) Table 76. I2C receive FIFO register (I2C_RFR)Add

I2C bus interface RM035284/138 DocID024647 Rev 110.2.7 I2C transmit FIFO threshold register (I2C_TFTR) Table 77. I2C transmit FIFO threshold r

DocID024647 Rev 1 85/138RM0352 I2C bus interface13710.2.9 I2C baud-rate counter register (I2C_BRCR) Table 79. I2C baud-rate counter register (

I2C bus interface RM035286/138 DocID024647 Rev 110.2.10 I2C interrupt mask set/clear register (I2C_IMSCR) Table 80. I2C interrupt mask set/cle

DocID024647 Rev 1 87/138RM0352 I2C bus interface137[23] SALM: slave arbitration lost mask. SALM enables the interrupt bit SAL. (SMBUS mode)0: SAL inte

I2C bus interface RM035288/138 DocID024647 Rev 110.2.11 I2C raw interrupt status register (I2C_RISR) Table 81. I2C raw interrupt status regist

DocID024647 Rev 1 89/138RM0352 I2C bus interface137• When set in slave mode: slave resets the communication and lines are released by hardware.• When

DocID024647 Rev 1 9/138RM0352 List of tables9Table 101. SSPCPSR register bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I2C bus interface RM035290/138 DocID024647 Rev 11: master arbitration lost.[23] SAL: slave arbitration lost (SMBUS mode). SAL is set when the slave lo

DocID024647 Rev 1 91/138RM0352 I2C bus interface1370: Tx FIFO is not empty.1: Tx FIFO is empty with the read-from-slave operation in progress.[16] RFS

I2C bus interface RM035292/138 DocID024647 Rev 110.2.12 I2C masked interrupt status register (I2C_MISR) Table 82. I2C masked interrupt status

DocID024647 Rev 1 93/138RM0352 I2C bus interface137Description: The I2CMISR register indicates the interrupt sources after masking. For the descripti

I2C bus interface RM035294/138 DocID024647 Rev 1Note: The reset value is valid only when I2C frequency equal to 48 MHz. If frequency changes the user

DocID024647 Rev 1 95/138RM0352 I2C bus interface13710.2.16 I2C setup time START condition F/S (I2C_TSUSTA_FST_STD) Table 86. I2C setup time ST

I2C bus interface RM035296/138 DocID024647 Rev 1 10.2.18 I2C peripheral identification register 0 (I2C_PERIPHID0)Table 88. I2C peripheral iden

DocID024647 Rev 1 97/138RM0352 I2C bus interface13710.2.20 I2C peripheral identification register 2 (I2C_PERIPHID2) Table 90. I2C peripheral i

I2C bus interface RM035298/138 DocID024647 Rev 110.2.22 I2C PCell identification register 0 (I2C_PCELLID0) Table 92. I2C PCell identification

DocID024647 Rev 1 99/138RM0352 I2C bus interface13710.2.24 I2C PCell identification register 2 (I2C_PCELLID2) Table 94. I2C PCell identificati