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SPI (serial peripheral interface) RM0352
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11 SPI (serial peripheral interface)
The SPI block is an IP provided by ARM (PL022 “PrimeCell
®
Synchronous Serial Port”).
Additional details about its functional blocks may be found in “ARM PrimeCell®
Synchronous Serial Port (PL022) Technical Reference Manual”.
11.1 Features
The SPI is a master or slave interface that enables synchronous serial communication with
slave or master peripherals having one of the following:
• A MOTOROLA SPI-compatible interface
• A TEXAS INSTRUMENTS synchronous serial interface
• A National Semiconductor MICROWIRE
®
interface.
The SPI interface operates as a master or slave interface. It supports bit rates up to 2 MHz
and higher in both master and slave configurations. The SPI has the following features:
• Parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location deep
transmit FIFO
• Serial-to-parallel conversion on received data, buffering it in a 16-bit wide, 8-location
deep receive FIFO
• Programmable data frame size from 4 to 16 bits
• Programmable clock bit rate and prescaler. The input clock may be divided by a factor
of 2 to 254 in steps of two to provide the serial output clock
• Programmable clock phase and polarity.
11.2 Clock prescaler
When configured as a master, an internal prescaler is used to provide the serial output
clock. The prescaler may be programmed through the SSPCPSR register to divide the
SSPCLK by a factor of 2 to 254 in steps of two. As least significant bit of the SSPCPSR
register is not used, division by an odd number is impossible and this ensures a symmetrical
(equal mark space ratio) clock is generated.
The output of this prescaler is further divided by a factor 1 to 256, through the programming
of the SSPCR0 control register, to give a final master output clock.
- Reference manual 1
- Contents 2
- DocID024647 Rev 1 3/138 3
- 4/138 DocID024647 Rev 1 4
- DocID024647 Rev 1 5/138 5
- 6/138 DocID024647 Rev 1 6
- List of tables 7
- 8/138 DocID024647 Rev 1 8
- DocID024647 Rev 1 9/138 9
- List of figures 10
- 1 Referenced document 11
- 2 System and memory overview 12
- 2.2 Memory organization 13
- 2.3 Embedded SRAM 15
- 2.4 Flash memory overview 15
- 2.5 Physical remap 16
- Interrupts RM0352 18
- Table 3. Interrupt vectors 18
- (continued) 18
- 5.1 Introduction 21
- 5.2 Clock generation 21
- Figure 2. Clock generation 22
- DocID024647 Rev 1 23/138 23
- 5.3 Reset generation 24
- 5.3.2 Power-on reset 25
- 5.3.3 ECC reset 25
- 5.3.4 Watchdog reset 25
- 5.3.5 System reset request 26
- 5.3.6 Lockup reset 26
- 5.3.7 Recall done 26
- 6.3.4 Command register 34
- MASS ERASE 34
- DocID024647 Rev 1 37/138 37
- 0-Unlocked 37
- 1NoLocked 37
- 1 Yes Unlocked 37
- Watchdog timer (WDG) RM0352 40
- Table 26. WDG register list 40
- dual timer module (SP804) 47
- 8.2 Functional overview 48
- DocID024647 Rev 1 49/138 49
- 8.2.2 Functional description 50
- Free running counter blocks 51
- Interface reset 51
- Prescaler operation 52
- Timer operation 53
- 54/138 DocID024647 Rev 1 54
- Interrupt behavior 55
- 56/138 DocID024647 Rev 1 56
- 8.3 Programmer's model 57
- 8.3.2 Register descriptions 59
- Load register, TimerXLoad 60
- ". 63
- 9.4 Configuring SysTick 70
- C bus interface RM0352 72
- Table 70. I 72
- C register list 72
- 74/138 DocID024647 Rev 1 74
- DocID024647 Rev 1 75/138 75
- 76/138 DocID024647 Rev 1 76
- 78/138 DocID024647 Rev 1 78
- 10.2.5 I 80
- C status register (I2C_SR) 80
- DocID024647 Rev 1 81/138 81
- 82/138 DocID024647 Rev 1 82
- DocID024647 Rev 1 87/138 87
- DocID024647 Rev 1 89/138 89
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- DocID024647 Rev 1 91/138 91
- 11.1 Features 100
- 11.2 Clock prescaler 100
- 101
- 11.5.4 SSPRTINTR 114
- 11.5.1 SSPRXINTR 114
- 11.5.2 SSPTXINTR 114
- 11.5.3 SSPRORINTR 114
- 12.1 Features 115
- 12.2 IrDA SIR block 116
- 12.3 Baud rate generator 116
- 12.4 Interrupts 116
- 12.4.1 UARTMSINTR 117
- 12.4.2 UARTRXINTR 117
- 12.4.3 UARTTXINTR 117
- 12.5 UART registers 118
- 12.6 Register descriptions 120
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