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dual timer module (SP804) RM0352
64/138 DocID024647 Rev 1
Timer peripheral ID1 register, TimerPeriphID1
The TimerPeriphID1 register is hard-coded and the fields in the register determine the reset
value.Table 58 lists the bit assignments of the register.
Timer peripheral ID2 register, TimerPeriphID2
The TimerPeriphID2 register is hard-coded and the fields in the register determine the reset
value. Table 59 lists the bit assignment of the register.
Timer peripheral ID3 register, TimerPeriphID3
The TimerPeriphID3 register is hard-coded and the fields in the register determine the reset
value. Table 60 shows the bit assignments of the register.
PrimeCell identification registers, TimerPCellID0-3
The TimerPCellID0-3 registers are four 8-bit registers, that span address locations 0xFF0-
0xFFC. The read-only registers can conceptually be treated as a 32-bit register. The register
is used as a standard cross-peripheral identification system. The TimerPCellID register is
set to 0xB105F00D. Figure 14 shows the bit assignment for the registers.
Table 58. Timer peripheral ID1 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:4] Designer0 These bits read back as 0x1
[3:0] PartNumber1 These bits read back as 0x8
Table 59. Timer peripheral ID2 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:4] Revision These bits read back as 0x1
[3:0] Designer1 These bits read back as 0x4
Table 60. TimerPeriphID3 register bit assignments
Bit Name Description
[31:8] - RESERVED, read undefined, must be written as zeros
[7:0] Configuration These bits read back as 0x00
- Reference manual 1
- Contents 2
- DocID024647 Rev 1 3/138 3
- 4/138 DocID024647 Rev 1 4
- DocID024647 Rev 1 5/138 5
- 6/138 DocID024647 Rev 1 6
- List of tables 7
- 8/138 DocID024647 Rev 1 8
- DocID024647 Rev 1 9/138 9
- List of figures 10
- 1 Referenced document 11
- 2 System and memory overview 12
- 2.2 Memory organization 13
- 2.3 Embedded SRAM 15
- 2.4 Flash memory overview 15
- 2.5 Physical remap 16
- Interrupts RM0352 18
- Table 3. Interrupt vectors 18
- (continued) 18
- 5.1 Introduction 21
- 5.2 Clock generation 21
- Figure 2. Clock generation 22
- DocID024647 Rev 1 23/138 23
- 5.3 Reset generation 24
- 5.3.2 Power-on reset 25
- 5.3.3 ECC reset 25
- 5.3.4 Watchdog reset 25
- 5.3.5 System reset request 26
- 5.3.6 Lockup reset 26
- 5.3.7 Recall done 26
- 6.3.4 Command register 34
- MASS ERASE 34
- DocID024647 Rev 1 37/138 37
- 0-Unlocked 37
- 1NoLocked 37
- 1 Yes Unlocked 37
- Watchdog timer (WDG) RM0352 40
- Table 26. WDG register list 40
- dual timer module (SP804) 47
- 8.2 Functional overview 48
- DocID024647 Rev 1 49/138 49
- 8.2.2 Functional description 50
- Free running counter blocks 51
- Interface reset 51
- Prescaler operation 52
- Timer operation 53
- 54/138 DocID024647 Rev 1 54
- Interrupt behavior 55
- 56/138 DocID024647 Rev 1 56
- 8.3 Programmer's model 57
- 8.3.2 Register descriptions 59
- Load register, TimerXLoad 60
- ". 63
- 9.4 Configuring SysTick 70
- C bus interface RM0352 72
- Table 70. I 72
- C register list 72
- 74/138 DocID024647 Rev 1 74
- DocID024647 Rev 1 75/138 75
- 76/138 DocID024647 Rev 1 76
- 78/138 DocID024647 Rev 1 78
- 10.2.5 I 80
- C status register (I2C_SR) 80
- DocID024647 Rev 1 81/138 81
- 82/138 DocID024647 Rev 1 82
- DocID024647 Rev 1 87/138 87
- DocID024647 Rev 1 89/138 89
- 90/138 DocID024647 Rev 1 90
- DocID024647 Rev 1 91/138 91
- 11.1 Features 100
- 11.2 Clock prescaler 100
- 101
- 11.5.4 SSPRTINTR 114
- 11.5.1 SSPRXINTR 114
- 11.5.2 SSPTXINTR 114
- 11.5.3 SSPRORINTR 114
- 12.1 Features 115
- 12.2 IrDA SIR block 116
- 12.3 Baud rate generator 116
- 12.4 Interrupts 116
- 12.4.1 UARTMSINTR 117
- 12.4.2 UARTRXINTR 117
- 12.4.3 UARTTXINTR 117
- 12.5 UART registers 118
- 12.6 Register descriptions 120
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